1. Field of the Invention
This invention relates to data processing systems, and more particularly, to means for continuously checking for failures in error checking logic.
2. Description of the Related Art
In U.S. Pat. No. 4,176,258 of Daniel Jackson, granted on Nov. 27, 1979 and assigned to Intel Corporation, detection of errors is accomplished by a redundancy method known as functional redundancy checking (FRC). In this method, an integrated circuit component is duplicated and output signals from the two identical components are compared in an FRC logic. An error condition is reported if the output signals do not match one another.
U.S. Pat. No. 4,792,955 of Johnson et al., granted on Dec. 20, 1988 and assigned to Intel Corporation, describes a way of recovering from an error detected by the FRC logic where one of the components is found to be faulty. This is done by splitting the components apart so that the faulty one is disengaged from the system and the operative one continues in use, but without the FRC checking capability.
In these prior circuits, if the FRC logic itself is not working correctly error conditions may go unreported. Because the FRC logic is what the system relies on to correctly identify errors, it is important that the FRC logic itself be tested during normal operation of the system. This need gave rise to U.S. Pat. No. 4,903,270 of Johnson et al., granted on Feb. 20, 1990 and assigned to Intel Corporation, which describes a redundant module checking system in which the error checking logic continuously performs a check on itself in order to ascertain that it is working correctly. This is accomplished by providing an integrated circuit module in which an error detection circuit compares data generated internally on the module with data generated externally from another substantially identical module. An error detect output is asserted upon the condition that data generated internally on module and data generated externally from module do not match. A circuit alters the internally generated data by injecting erroneous data into the internally generated data to thereby generate altered data. An error anticipation control logic generates a test condition, which corresponds to the expected error condition caused by the altered data. A comparison circuit compares the actual error detect output with the expected error detect output. An error output is asserted if the actual error detect output and the expected error detect output do not match. This circuit has the advantage that malfunctions in error detection circuitry can be detected during normal operation of the components. The disadvantage is that for some time the test circuitry could induce many other errors that could mask whether the FRC is working correctly.
It is an object of the invention to provide a circuit which is uniform across all pins being checked and that will check the checking circuitry but will not induce other errors that mask whether the FRC is working correctly.
It is a further object of the invention to provide a circuit that will check the output
It is a further object of the invention to provide a circuit that will check the output pins of a chip to ensure that the output drivers actually drove the data presented to them.